1. Field
Example embodiments of the inventive concepts relate to electronic devices, and more particularly, to memory devices and read error correction methods thereof.
2. Description of the Related Art
Typically, a semiconductor memory device may be classified as either a volatile memory or a nonvolatile memory. For example, a volatile memory may be a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM)). A nonvolatile memory may be, for example, a Ferroelectric Random Access Memory (FRAM), a Phase change Random Access Memory (PRAM), a Magnetoresistive Random Access Memory (MRAM) and/or a flash memory. A volatile memory may lose stored data when a power supply source is shut off. A nonvolatile memory may retain stored data even though the power supply source is shut off. Because a flash memory may have a high programming speed, may consume low power and may store large-scale data, it is widely used as a storage medium in computer systems.
Flash memory may be divided into a NOR type and a NAND type according to a connection state between a cell and a bit line. A NOR-type flash memory may have two or more cell transistors connected to one bit line in parallel, may store data using channel hot electron injection and may erase data using Fowler-Nordheim tunneling. A NAND-type flash memory may have two or more cell transistors connected to one bit line in series, and may store and erase data using Fowler-Nordheim tunneling.
Each memory cell may store 1-bit data and/or multi-bit data. In a case where 1-bit data is stored in one memory cell, the memory cell may have a threshold voltage corresponding to one of two threshold voltage states, for example, a data 1 and a data 0. In a case where 2-bit data is stored in one memory cell, the memory cell may have threshold voltages belonging to any one of four threshold voltage states. In a case where a 3-bit data is stored in one memory cell, the memory cell may have threshold voltages belonging to any one of eight threshold voltage states. Recently, research is being actively made into various technologies for storing 4-bit or greater data in one memory cell.
Because of increased integration density and the provision of multi-level cell (MLC) technology, interference between the cells of a flash memory device may increase and the read margin between threshold voltage distributions may be reduced. In highly integrated memory cells, because an oxide layer may be deteriorate as a number of program/erase cycles (P/E cycle) of the oxide layer increases, the life of a memory device may be shortened. Accordingly, research is being actively conducted into ensuring the life of a flash memory device and the reliability of stored data.